Taha Abdelazziz Rahmani

2026

1. MICPRO

   NET4EXA: Toward Ethernet-native interconnects for exascale HPC and AI systems

   John Gliksberg, Luca Andreetti, Daniele Di Bari, and 53 more authors

   Microprocessors and Microsystems, 2026

   Abs Bib

   High-Performance Computing (HPC) and Artificial Intelligence (AI) infrastructures are evolving toward highly heterogeneous exascale systems, where communication scalability and data movement increasingly limit overall performance and efficiency. This paper presents NET4EXA, a European initiative targeting the development of BXIv3, the third generation of the Bull eXascale Interconnect (BXI), based on an Ethernet-native architecture combining FPGA-based SmartNICs, custom switching ASICs, and hardware-accelerated communication semantics. The paper reports a selection of mid-project research results spanning multiple layers of the communication stack, including NIC- and switch-level collective offloading, TCP/RDMA acceleration, on-NIC processing, communication–computation overlap through triggered operations, and optimized data movement using IOVEC mechanisms. Additional contributions include OpenSHMEM integration over a Portals-based runtime, congestion-aware routing and mapping strategies for Dragonfly＋ topologies, and benchmarking frameworks for HPC and AI communication workloads. Finally, the paper discusses emerging research directions toward future interconnect architectures based on silicon photonics and co-packaged optics targeting multi-terabit communication systems.

   @article{GLIKSBERG2026105296,
     title = {NET4EXA: Toward Ethernet-native interconnects for exascale HPC and AI systems},
     journal = {Microprocessors and Microsystems},
     pages = {105296},
     year = {2026},
     issn = {0141-9331},
     doi = {https://doi.org/10.1016/j.micpro.2026.105296},
     url = {https://www.sciencedirect.com/science/article/pii/S0141933126000530},
     author = {Gliksberg, John and Andreetti, Luca and Bari, Daniele Di and Pagano, Giuseppe and Monterubbiano, Andrea and Turisini, Matteo and Zaourar, Lilia and Benazouz, Mohamed and Pottier, Antony and Takhoubit, Khaled and Jaeger, Julien and Beaulieu, Corentin and Peysieux, Anis and Reynier, Florian and Taboada, Hugo and Bilas, Angelos and Chaix, Fabien and Chrysos, Nikolaos and Mageiropoulos, Evangelos and Moreau, Gilles and Ammendola, Roberto and Biagioni, Andrea and Chiarini, Carlotta and Frezza, Ottorino and {Lo Cicero}, Francesca and Lonardo, Alessandro and Martinelli, Michele and Paolucci, Pier Stanislao and Pastorelli, Elena and Perticaroli, Pierpaolo and Pontisso, Luca and Rossi, Cristian and Simula, Francesco and Vicini, Piero and Mocholi, Samuel Rodrigo and Vallero, Marzio and Fan, Kaijie and Fiore, Sandro Luigi and Granelli, Fabrizio and Pasquali, Thomas and Patrignani, Marco and Pezzuto, Simone and Pichetti, Lorenzo and Potestio, Raffaello and Raffi, Jacopo and Siracusa, Domenico and Tubiana, Luca and Velha, Philippe and Vella, Flavio and {De Sensi}, Daniele and Fazzari, Francesco and Paschali, Vladimiro and Pasqualoni, Saverio and Piarulli, Lorenzo and Pontarelli, Salvatore and Rahmani, Taha Abdelazziz},
     keywords = {High-performance interconnects, Exascale computing, SmartNIC, RDMA, HPC and AI systems},
   }

2. Euro-Par26

   Fairness Implications of Ultra Ethernet Congestion Control in Datacenters

   Taha Abdelazziz Rahmani, Daniele De Sensi, and Salvatore Pontarelli

   In Euro-Par 2026 Poster Session, 2026

   Bib

   @inproceedings{fairness-ultra-ethernet,
     author = {Rahmani, Taha Abdelazziz and De Sensi, Daniele and Pontarelli, Salvatore},
     title = {Fairness Implications of {Ultra Ethernet} Congestion Control in Datacenters},
     year = {2026},
     booktitle = {Euro-Par 2026 Poster Session},
     doi = {To Appear},
   }