Elia Belli

2026

1. SC26

   High-Performance Tensor Formulation of the Viterbi Algorithm for Hidden Semi-Markov Models

   Lorenzo Piarulli, Elia Belli, and Daniele De Sensi

   In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’26), Nov 2026

   Abs Bib

   Hidden Semi-Markov Models (HSMMs) are fundamental probabilistic models widely adopted across diverse domains, from computational biology to finance and signal processing. The Viterbi algorithm decodes the most likely state sequence given an HSMM and can be applied iteratively for ab initio model learning. However, existing Viterbi implementations remain sequential, and GPU-accelerated solutions are entirely absent, making HSMM decoding impractical for large-scale workloads. We present a tensor-based formulation of the Viterbi algorithm for HSMMs, restructuring the inner loops into tensor operations that naturally map onto SIMD units and massively parallel architectures. Building on this formulation, we provide optimized implementations spanning single- and multi-core CPUs, and, for the first time, GPU. Experimental evaluation demonstrates speedups of up to 14× on a single core, over 200× with multi-core, and over 570× on GPU over the state-of-the-art sequential baseline, establishing a new performance baseline for large-scale HSMM decoding.

   @inproceedings{tensor-viterbi,
     author = {Piarulli, Lorenzo and Belli, Elia and De Sensi, Daniele},
     title = {High-Performance Tensor Formulation of the Viterbi Algorithm for Hidden Semi-Markov Models},
     year = {2026},
     month = nov,
     booktitle = {Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC'26)},
     doi = {To Appear},
   }

2. arXiv

   Stencil Computations on Cerebras Wafer-Scale Engine

   Elia Belli and Daniele De Sensi

   May 2026

   Abs arXiv Bib

   Stencil computations are a fundamental kernel in scientific computing, critical for simulations in domains such as fluid dynamics and climate modeling. However, these computations are often memory-bound on traditional High-Performance Computing architectures like GPUs, struggling against the "Memory Wall". Simultaneously, the rise of AI-oriented hardware, such as the Cerebras Wafer-Scale Engine, offers massive core parallelism and high-bandwidth on-chip memory, though typically optimized for lower-precision workloads. This work investigates the viability of bridging this divergence by mapping stencil algorithms onto the Cerebras WSE-3. The study introduces CStencil, a novel framework designed to implement two-dimensional stencil computations on the WSE-3. To ensure a rigorous and fair performance evaluation, the research also adapts ConvStencil, a state-of-the-art GPU stencil solver, porting it from its original double-precision design to single-precision for execution on an NVIDIA A100 GPU. Experimental results show that the WSE-3’s distributed SRAM and mesh interconnect effectively eliminate the off-chip memory bottlenecks common in GPU implementations. CStencil achieves speedups of up to 342x over the adapted ConvStencil version. A roofline model analysis further confirms that CStencil saturates the available compute and memory resources, demonstrating that the WSE dataflow architecture can be successfully repurposed for traditional scientific algorithms. These findings highlight the potential of the WSE-3 to deliver hardware utilization levels unattainable on conventional systems, offering a promising path toward overcoming the memory limitations of current HPC architectures.

   @misc{cstencil-cerebras,
     author = {Belli, Elia and De Sensi, Daniele},
     title = {Stencil Computations on {Cerebras} Wafer-Scale Engine},
     year = {2026},
     month = may,
     doi = {10.48550/arXiv.2605.07954},
     url = {https://arxiv.org/abs/2605.07954},
   }